1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a circuit and method for controlling a sense amplifier of a semiconductor memory apparatus.
2. Related Art
Semiconductor memory apparatuses include sense amplifiers for amplifying a minute voltage difference between a bit line and a bit bar (/bit) line in a core area and reading data recorded on corresponding memory cells and control circuits for controlling the operation of the sense amplifiers.
As shown in FIG. 1, a sense amplifier control circuit of a semiconductor memory apparatus according to the related art includes: a delay unit 10 that delays a bank active signal BA_ACT by a predetermined delay time td and outputs the delayed signal; a driving signal generating unit 20 that generates driver driving signals SAP1, SAP2, and SAN for determining the operation timing of a sense amplifier driver 30 according to an output signal BA_ACTd of the delay unit 10; and the sense amplifier driver 30 that outputs sense amplifier driving signals RTO and SB according to the driver driving signals SAP1, SAP2, and SAN to drive a sense amplifier 40.
The delay time of the delay unit 10 is determined when a circuit is designed, and has a fixed value.
As shown in FIG. 2, the driving signal generating unit 20 includes: an inverting delay 21 that receives the bank active signal BA_ACT; a first NAND gate ND1 that receives the bank active signal BA_ACT and an output signal SA_ovd of the inverting delay 21; a first inverter IV1 that receives the output of the first NAND gate ND1 and outputs the driver driving signal SAP1; a second NAND gate ND2 that receives the output of the first NAND gate ND1 and the bank active signal BA_ACT; a second inverter IV2 that receives the output of the second NAND gate ND2 and outputs the driver driving signal SAP2; a third inverter IV3 that receives the bank active signal BA_ACT; and a fourth inverter IV4 that receives the output of the third inverter IV3 and outputs the driver driving signal SAN.
As shown in FIG. 3, the sense amplifier driver 30 includes: a first transistor N1 having a source to which an external voltage Vext is applied and a gate to which the driver driving signal SAP1 is input; a second transistor N2 having a source to which a core voltage Vcore is applied and a gate to which the driver driving signal SAP2 is input; a third transistor N3 having a source that is connected to the drains of the first and second transistors N1 and N2; a fourth transistor N4 having a source connected to a drain of the third transistor N3, a gate to which the driver driving signal SAN is input, and a drain connected to the ground; a fifth transistor N5 having a drain connected to a node between the first transistor N1 and the third transistor N3; and a sixth transistor N6 having a drain connected to a node between the third transistor N3 and the fourth transistor N4. A bit line equalizing signal bleq is input to the gates of the third, fifth, and sixth transistors N3, N5, and N6. A bit line precharge voltage Vblp is applied to the sources of the fifth and sixth transistors N5 and N6. The sense amplifier driving signals RTO and SB are output from a node between the first transistor N1 and the fifth transistor N5 and a node between the fourth transistor N4 and the sixth transistor N6, respectively.
Next, the operation of the sense amplifier control circuit of the semiconductor memory apparatus according to the related art will be described with reference to FIG. 4.
When the bank active signal BA_ACT is activated at a high level, the output signal BA_ACTd of the delay unit 10 is activated at a high level after the elapse of the delay time td. The delay time td has a fixed value.
When the output signal BA_ACTd of the delay unit 10 is activated at the high level, the driving signal generating unit 20 activates the driver driving signals SAN and SAP1 at a high level and outputs the activated signals.
Since the output signal BA_ACTd of the delay unit 10 is activated at the high level, the driver driving signal SAP1 is inactivated at a low level according to an output signal SA_ovd of the inverting delay 21 of the driving signal generating unit 20, and the driver driving signal SAP2 is activated at a high level.
When the bank active signal BA_ACT is inactivated at a low level, the driver driving signals SAN and SAP2 are inactivated at a low level.
The sense amplifier driver 30 outputs the sense amplifier driving signals RTO and SB according to the driver driving signals SAP1, SAP2, and SAN to drive the sense amplifier 40.
That is, the semiconductor memory apparatus does not perform an active operation (for example, reading) during a precharge period for which the bank active signal BA_ACT is at a low level. Therefore, the bit line precharge voltage Vblq is used to maintain the bit line and the bit bar line at the same level.
Since all of the driver driving signals SAP1, SAP2, and SAN are at low levels during the precharge period, the first, second, and fourth transistors N1, N2, and N4 are turned off, so that the operation of the sense amplifier 30 stops.
Meanwhile, the semiconductor memory apparatus performs an active operation (for example, reading) during an active period for which the bank active signal BA_ACT is at a high level. Therefore, the bit line equalizing signal bleq is inactivated at a low level, and the third, fifth, and sixth transistors N3, N5, and N6 are turned off. As shown in FIG. 4, when the driver driving signals SAP1, SAP2, and SAN are activated at predetermined timings, the first, second, and fourth transistors N1, N2, and N4 are turned on. Then, the sense amplifier driver 30 operates to output the sense amplifier driving signals RTO and SB.
The sense amplifier control circuit of the semiconductor memory apparatus according to the related art has the following problems because it drives the sense amplifier to perform a data sensing operation at a fixed delay timing.
First, when an external voltage level is higher than a reference voltage level that is set on the basis of the delay value, a signal waveform varies rapidly. However, the driver driving signal of the driving signal generating unit 20 does not correspond to the rapid variation in the signal waveform, but is generated at a predetermined timing. Therefore, the sense amplifier driving signal of the sense amplifier driver 30 is also generated at a delayed timing, such that the sense amplifier 40 has an insufficient data sensing time, which causes a data sensing error.
Second, when the external voltage level is lower than the reference voltage level that is set on the basis of the delay value, a signal waveform varies slowly. However, the driver driving signal of the driving signal generating unit 20 does not correspond to the slow variation in the signal waveform, but is generated at a predetermined timing. Therefore, the sense amplifier driving signal of the sense amplifier driver 30 is also generated at the timing earlier than the predetermined timing, so that the sense amplifier 40 has an unnecessary extra data sensing time, which causes a data sensing error in the semiconductor memory apparatus.